Coding method and apparatus

ABSTRACT

A parallel concatenated coder (20) outputs a sequence of data sets in which earlier data sets contain data bits (d) and non-interleaved parity bits (p) without interleaved parity bits (q), while later data sets include the interleaved parity bits (q). Each data set is modulated as one symbol. The output format partially overcomes the delay incurred by interleaving the parity bits (q), with a substantially even distribution of data and parity bits in the sequence of data sets. The delay may be reduced further by interleaving with an index constraint.

TECHNICAL FIELD

The present invention relates to a coding method and apparatus involvingparallel concatenated codes linked by an interleaver, for use inwireless digital transmission.

BACKGROUND ART

Parallel concatenated convolutional codes, known as ‘Turbo’ codes, havebeen disclosed in the paper ‘Near Shannon Limit Error-Correcting Codingand Decoding: Turbo-Codes(1)’, Berrou, Glavieux and Thitimajshima,ICC'93 Geneva, May 23-26, 1993, as well as in U.S. Pat. No. 5,446,747.This type of code has attracted much attention in the digitaltransmission field because of its bit error rate performance close tothe Shannon limit. The Turbo encoder as originally proposed consists oftwo recursive systematic convolutional coders. The two encoders receivethe same information bits, but the input of one of the encoders isconnected to an interleaver so that the order of the input bits isscrambled.

Parallel concatenated encoders using constituent codes other thanconvolutional codes have also been proposed, for example in the article‘Unveiling Turbo Codes: Some Results on Parallel Concatenated CodingSchemes’ by Benedetto and Montorsi, IEEE Transactions on InformationTheory, Vol. 42, No. 2, March 1996, and in ‘Iterative Decoding of TurboCodes and Other Concatenated Codes’, a dissertation dated February 1996,by S. A. Barbulescu of the Institute of Telecommunications Research,University of South Australia.

However, the use of the interleaver in Turbo and related codes resultsin a long encoding delay, which has prevented their adoption in realtime applications such as digital mobile telephony (see the article byBenedetto and Montorsi cited above).

STATEMENT OF THE INVENTION

According to the present invention, there is provided a parallelconcatenated encoder which generates a sequence of data sets fortransmission. Interleaved parity bits are not included in earlier datasets, which contain data bits and non-interleaved parity bits. As aresult, the delay incurred by interleaving the interleaved parity bitsis not fully incurred in the output of the sequence of data sets as awhole; at the same time, uneven distribution of data bits and paritybits is avoided in a substantial part of the sequence.

In some embodiments of the invention, the interleaved parity bits havean index constraint substantially less than the size of the interleaver.This allows interleaved parity bits to be output before all of the databits have been stored in the interleaver, further reducing the delayincurred by the encoder, without significantly increasing the bit errorrate over a transmission channel.

BRIEF DESCRIPTION OF THE DRAWINGS

Specific embodiments of the present invention will now be described withreference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a satellite communications system;

FIG. 2 is a schematic diagram of an earth station in the system of FIG.1;

FIG. 3 is a schematic diagram of a turbo encoder in the earth station ofFIG. 2;

FIG. 4 shows the features of the buffer of FIG. 3;

FIG. 5 is a diagram of the modulation scheme implemented by themodulator of the earth stations;

FIG. 6 is a diagram of the transmission frame format used by the earthstations;

FIG. 7 is a diagram of the delay incurred in transmission of a frameover the satellite link in a conventional or known output format;

FIG. 8 is a diagram of the order of transmission of bits from theencoder in a first embodiment of the present invention;

FIG. 9 is a diagram of the order of transmission of bits from theencoder in a second embodiment of the present invention;

FIG. 10 is a diagram of the order of transmission of bits from theencoder in a third embodiment of the present invention; and

FIG. 11 is a diagram of the order of transmission of bits from theencoder in a fourth embodiment of the present invention.

MODES FOR CARRYING OUT THE INVENTION

As shown in FIG. 1, mobile terminal equipment 4 is connected to a mobileearth station (MES) 6. The mobile terminal equipment 4 may comprisetelephone equipment, facsimile equipment or data terminal equipment, andmay include interface equipment for allowing telephone, facsimile ordata terminals designed for connection to other types of network to beconnected to the satellite network. Examples of such interface equipmentare described in GB 2286739, U.S. Pat. No. 5,587,810, GB 2300540, and WO97/00561. The mobile terminal equipment 4 sends digital data to the MES6 for RF modulation and transmission to a satellite 8, and the MES 6receives and demodulates digital data from the satellite 8, thedemodulated data then being sent to the mobile terminal equipment 4.

The satellite 8 carries a transponder which receives modulated signals,converts them to an intermediate frequency, amplifies them andretransmits them at a different frequency from the received frequency.The satellite 8 thereby links the MES 6 to a land earth station (LES)10, so that signals transmitted by the MES 6 are received by the LES 10and vice versa, via the satellite 8.

The LES 10 is connected to a network interface 12 for providing aninterface to a network 14, in this case a PSTN. A call is therebyconnected over the network 14 to fixed terminal equipment 16, whichcomprises telephone, facsimile or data terminal equipment compatiblewith the mobile terminal equipment 4.

FIG. 2 shows the relevant functional sections of both the MES 6 and theLES 10 in more detail. The functions of the MES 6 and the LES 10 aredistinct in other respects, but for convenience the same diagram andreference numerals are used for the relevant sections of both.

Digital data received from the mobile terminal equipment 4 or networkinterface 12 is encoded by an encoder 20 and then modulated by amodulator 24. The modulated output is transmitted by an antenna assembly28. Signals received from the antenna assembly 28 are demodulated by ademodulator 30 to generate digital data which is decoded by a decoder34. The output of the decoder 34 is connected to the mobile terminalequipment 4 or network interface 12. The operation of the functionalsections is controlled by a controller 36.

The encoder 20 is a Turbo encoder of the type shown in FIG. 3. Data bitsd_(k) are input to a first encoder ENC1, and to an interleaver 21, theoutput of which is connected to a second encoder ENC2. Each encoder ENC1and ENC2 is a recursive convolutional coder comprising four intermediatebinary stores D1 to D4, and binary adders or exclusive-OR gates. Witheach cycle, the contents of each of the binary stores D1 to D3 isshifted to binary stores D2 to D4 respectively, while the new contentsof D1 are derived from the previous contents of D2 to D4. The outputp_(k) from the first encoder and the output q_(k) from the secondencoder are derived from the contents of the binary stores D1, D2 and D4and from the input to the binary store D1.

The data bits d_(k), the non-interleaved parity bits p_(k) and theinterleaved parity bits q_(k) are output to a buffer 23 from which setsof bits (u₁, u₂, u₃, u₄) are output in parallel in accordance with apuncturing format, examples of which are described below.

As shown in FIG. 4, the buffer 23 comprises memory stores S_(d), S_(p)and S_(q) for the data bits d, non-interleaved parity bits p andinterleaved parity bits q respectively. Data and parity bits are readout of the memory stores S from addresses indicated by first and secondpointers P_(d1), P_(d2), P_(p1), P_(p2), P_(q1), P_(q2) for each of thememory stores S_(d), S_(p) and S_(q) respectively and output as aselected one of the output bits u₁, u₂, u₃, u₄ determined by amultiplexer 25. The sequence of addresses from which the data and paritybits are read out and the sequence of settings of the multiplexertogether determine the transmission format of the data and parity bitsand the puncturing scheme of the parity bits, not all of which aretransmitted. The arrangement shown in FIGS. 3 and 4 is a functionalrepresentation of the turbo encoder and may be implemented entirely in asuitably programmed digital signal processor (DSP).

In a conventional format, the outputs of the encoder 20 are rate halfpunctured and modulated as follows. At each clock cycle, the systematicdata bit d_(k) is selected as output together with an alternating one ofthe parity bits p_(k), q_(k). The parity bit which is not selected isdiscarded. The output data bits and parity bits for each pair of clockcycles are modulated as one symbol in a 16 QAM (16 quadrature amplitudemodulation) scheme.

The conventional format is represented in Table 1 below.

TABLE 1 Cycle 1 2 3 4 data d_(k) d₁ d₂ d₃ d₄ parity p_(k) p₁ — p₃ —parity q_(k) — q₂ — q₄ 16QAM Symbol (d₁, p₁, d₂, q₂) (d₃, p₃, d₄, q₄)

Each symbol is formed from the four bits (u₁, u₂, u₃, u₄) with the bitsu₁, u₂ modulating the I (amplitude) component and the bits u₃, u₄modulating the Q (phase) component such that:

A_(i)=[u₁, u₂]→I

B_(j)=[u₃, u₄]→Q

The modulation scheme, as shown in FIG. 5, is square 16 QAM, although acircular 16 QAM scheme may be used. The data bits u₁, u₃ are the mostprotected in the 16 QAM symbol.

The symbols are transmitted in a frame format as shown in FIG. 6. Datais transmitted in a single channel per carrier (SCPC) channel format.The start of a data sequence is indicated by a preamble P and a uniqueword UW to aid acquisition of the channel. The data is then transmittedin frames F₁ to F_(n) each consisting of 16 QAM symbols interspersedwith PSAM (pilot symbol assisted modulation) blocks PS, to allowmeasurement of fading and noise variance, so as to assist in decoding.At the end of each frame is a framing bit pattern FB. Encoded in thesymbols of each frame are two turbo-coded sub-frames C₁ and C₂corresponding to two unencoded sub-frames S₁ and S₂. The end of the datasequence is indicated by an end of data signal EOD.

The size of the interleaver 21 of the encoder 20 is equal to that of thesubframes S₁ and S₂. In one example, the interleaver 21 is a randominterleaver in which an entire block is loaded into the interleaver 21and the contents are then output in a pseudo-random order. In this case,the entire contents of one of the subframes S₁ or S₂ are loaded into theinterleaver 21 before the parity bits q_(k) are output. Hence, the delayincurred by the encoder 20 is at least N, where N is the time taken toreceive the number of bits in one of the subframes S₁ or S₂. The delayis shown graphically in FIG. 7, with time on the horizontal axis. In theencoder output, the different bits (u₁, u₂, u₃, u₄) are indicated on thevertical axis.

In accordance with embodiments of the present invention, the delayincurred by the encoder 20 is reduced to a fraction of the delay N inthe scheme described above, by rearranging the order of transmission ofthe data bits d and the parity bits p and q. Each embodiment is shownusing a rate half turbo code, although other rates may be used.

In a first embodiment, as shown in FIG. 8, the parity bits p are outputin the first half of a subframe C and the interleaved parity bits q areoutput in the second half of the subframe C. Note that the interleavedparity bits q are only output once all of the data bits d have beenreceived, but the delay involved is reduced to N/2 because twointerleaved parity bits q are transmitted per symbol, since all theparity bits p have already been transmitted.

In a second embodiment shown in FIG. 9, all of the data bits d and theparity bits p are transmitted before the interleaved parity bits q.During the first quarter of the subframe C, only the data bits d aretransmitted; during the middle half of the subframe C, data bits andparity bits p are transmitted; during the final quarter of the subframeC, only the interleaved parity bits q are transmitted. Hence, the delayis reduced to N/4 because four interleaved parity bits q are transmittedper symbol. However, half of the data bits d in the first quarter of thesubframe C are transmitted as the less protected bits (U2, U4) of the 16QAM symbols, leading to an increase in bit error rate relative to thefirst embodiment. Moreover, since the distribution of data bits d andparity bits p, q is uneven throughout the subframe C, the format isparticularly susceptible in fading channels with a fade rate comparableto the subframe rate. In such a case, the data bits in the first quarterof the subframe C may repeatedly coincide with the fading, giving a highbit error rate.

In the third and fourth embodiments described below, the interleaver 21is subject to an index constraint such that:${{\max\limits_{i}{{i - {\pi (i)}}}} \leq {\frac{N}{2}\quad i}} = {{0\quad \ldots \quad N} - 1}$

where i is the order of a data bit input to the interleaver 21 and π(i)is the corresponding output order. As a result, it is possible to beginoutput of the interleaved parity bits after only N/2 data bits have beeninput into the interleaver 21. The index constraint has a small effecton the bit error rate performance, but gives greater flexibility in theformat of the subframe C, as shown below.

In a third embodiment of the present invention, as shown in FIG. 10, thedata bits d are evenly distributed throughout the subframe C and alwaysoccupy the two most protected bit positions of the 16 QAM symbol. In thefirst quarter of the subframe C, the first half of the non-interleaveddata bits p occupy 2 bits per symbol; in the middle half, the secondhalf of the non-interleaved parity bits p and the first half of theinterleaved parity bits q each occupy one bit per symbol; in the finalquarter, the second half of the interleaved parity bits q occupy twobits per symbol. The resultant delay is N/4 bits, as in the secondembodiment, but the problems of less protected data bits d and unevendistribution of data bits and parity bits are avoided.

In a fourth embodiment of the present invention, as shown in FIG. 11,the effective delay is reduced to N/8, at the expense of thedisadvantages of the second embodiment. In the first eighth of thesubframe C, all four bit positions of the symbol are occupied by databits d. In the next quarter, the two most protected bit positions areoccupied by data bits d, while the two less protected bit positions areoccupied by the non-interleaved parity bits p. In the next half, the twomore protected bit positions are also occupied by data bits d, while oneeach of the less protected bit positions are occupied by thenon-interleaved parity bits p and the interleaved parity bits q. In thefinal eighth of the subframe C, all of the bit positions are occupied bythe interleaved parity bits q.

In the decoder 34, the bits are demodulated and a probability isestimated for each bit. The demodulated bits are separated into databits d, non-interleaved parity bits p and interleaved parity bits qaccording to the format used for transmission. The bits are then decodedusing a MAP decoder, of the type known from example from ‘Implementationand performance of a serial MAP decoder for use in an iterative turbodecoder’, S. S. Pietrobon, IEEE Int. Symp. Inform. Theory, Whistler,British Columbia, Canada, September 1995.

Modifications of the above embodiments may be envisaged within the scopeof the present invention. For example, alternative modulation schemesmay be used, such as 8 PSK (8 phase shift keying). Alternative ratecodes may be produced, by using different puncturing rates. Althoughrecursive convolutional codes are preferred as the constituent codes ofthe encoder 20, other constituent codes such as block codes may be used.The data bits d may be pre-coded before being input to the encoder 20,and/or further encoded after being output from the buffer 21.

The above embodiments are provided purely by way of example, and furthermodifications may be envisaged without departing from the scope of theappended claims.

What is claimed is:
 1. A coding and modulation method for digital data,comprising: receiving an input sequence of data bits; encoding sad inputsequence to generate a first encoded sequence of data bits; interleavingsaid input sequence to create an interleaved sequence of data bits;encoding said interleaved sequence of data bits to generate a secondencoded sequence of data bits; and modulating a sequence of data setseach including at least one of a data bit derived from said inputsequence, a first parity bit derived from said first encoded sequenceand a second parity bit derived from said second encoded sequence,wherein during an earlier period each of a plurality of said data setsincludes at least one said data bit and one said first parity bit butdoes not include any said second parity bits, and during a later periodeach of a plurality of said data sets includes at least one said secondparity bit.
 2. A method as claimed in claim 1, wherein during said laterperiod each said data set includes one or more said data bits and one ormore said second parity bits.
 3. A method as claimed in claim 2, whereinduring said later period each said data set includes one or more saidfirst parity bits.
 4. A method as claimed in claim 1 wherein in a firstperiod preceding said earlier period each said data set includes one ormore said data bits and does not include any said first or second paritybits.
 5. A method as claimed in claim 1 wherein in a last periodsubsequent to said later period each said data set includes one or moresaid second parity bits and does not include any said first parity bits.6. A method as claimed in claim 5, wherein in said last period each saiddata set does not include any said data bits.
 7. A method as claimed inclaim 1, wherein the step of modulating comprises outputting a sequenceof modulation states, each corresponding to a state of one of said datasets.
 8. A method as claimed in claim 7, wherein said data setscorrespond to said modulation states such that, when said data setincludes both at least one said data bit and said at least one first orsecond parity bit, said at least one data bit is more protected thansaid at least one first or second parity bit.
 9. A method as claimed inclaim 1, wherein said interleaving step is performed such that the orderof any bit of said interleaved sequence differs from the order of thecorresponding bit of said input sequence by less than a predeterminednumber, said predetermined number being substantially less than thenumber of bits in an interleaver in which the input sequence is storedfor interleaving.
 10. A method as claimed in claim 1 wherein said firstencoded sequence and said second encoded sequence are each encoded bymeans of a recursive convolutional coding algorithm.
 11. Apparatus formodulating digital data, comprising: a first encoder for encoding aninput sequence of data bits to generate a first encoded sequence of databits; an interleaver for interleaving said input sequence of data bitsto generate an interleaved sequence of data bits; a second encoder forencoding said interleaved sequence of data bits to generate a secondencoded sequence of data bits; and a modulator for modulating a sequenceof data sets each including at least one of a data bit derived from saidinput sequence, a first parity bit derived from said first encodedsequence and a second parity bit derived from said second encodedsequence, such that during an earlier period each of a plurality of saiddata sets includes at least one said data bit and one said first paritybit but does not include any said second parity bits, and during a laterperiod each of a plurality of said data sets includes at least one saidsecond parity bit.
 12. Apparatus as claimed in claim 11, wherein themodulator is operable such that during said later period each said dataset includes one or more said data bits and one or more said secondparity bits.
 13. Apparatus as claimed in claim 12, wherein the modulatoris operable such that during said later period each said data setincludes one or more said first parity bits.
 14. Apparatus as claimed inclaim 11, wherein the modulator is operable such that in a first periodpreceding said earlier period each said data set includes one or moresaid data bits and does not include any said first or second paritybits.
 15. Apparatus as claimed in claim 11, wherein the modulator isoperable such that in a last period subsequent to said later period eachsaid data set includes one or more said second parity bits and does notinclude any said first parity bits.
 16. Apparatus as claimed in claim15, wherein the modulator is operable such that in said last period eachsaid data set does not include any said data bits.
 17. Apparatus asclaimed in claim 11, wherein the modulator is operable to output asequence of modulation states, each corresponding to a state of one ofsaid data sets.
 18. Apparatus as claimed in claim 17, wherein said datasets correspond to said modulation states such that, when said data setincludes both said at least one data bit and said at least one first orsecond parity bit, said at least one data bit is more protected thansaid at least one first or second parity bit.
 19. Apparatus as claimedin claim 11, wherein said interleaver is arranged such that the order ofany bit of said interleaved sequence differs from the order of thecorresponding bit of said input sequence by less than a predeterminednumber, said predetermined number being substantially less than thenumber of bits in an interleaver in which the input sequence is stored.20. Apparatus as claimed in claim 11, wherein said first and secondencoders are each arranged to perform a recursive convolutional codingalgorithm.
 21. A satellite earth station including apparatus as claimedin claim
 11. 22. A method of modulating a systematic code word includingdata bits and interleaved parity bits derived from said data bits via anintermediate interleaving step, wherein the modulation of the first ofsaid parity bits is delayed by a plurality of modulation symbol periodsrelative to that of the first of said data bits, and the period overwhich the data bits are modulated overlaps the period over which theparity bits are modulated.
 23. Apparatus for modulating a systematiccode word including data bits and interleaved parity bits derived fromsaid data bits via an intermediate interleaving step, characterised bymeans for delaying the modulation of the first of said parity bits by aplurality of modulation symbol periods relative to that of the first ofsaid data bits, such that the period over which the data bits aremodulated overlaps the period over which the parity bits are modulated.